A typical computer system has at least a microprocessor and memory. The microprocessor processes, i.e., executes, instructions to accomplish various tasks of the computer system. Such instructions, along with the data required by the microprocessor when executing these instructions, are stored in some form of memory. FIG. 1 shows a typical computer system having a microprocessor (10) and some form of memory (12). The microprocessor (10) has, among other things, a central processing unit (also known and referred to as xe2x80x9cCPUxe2x80x9d or xe2x80x9cexecution unitxe2x80x9d) (14) and a memory controller (also known as xe2x80x9cload/store unitxe2x80x9d) (16). The CPU (14) is where the actual arithmetic and logical operations of the computer system take place. To facilitate the execution of operations by the CPU (14), the memory controller (16) provides the CPU (14) with necessary instructions and data from the memory (12). The memory controller (16) also stores information generated by the CPU (14) into the memory (12).
Memory, as shown in FIG. 1, is typically formed by numerous storage cells, where each storage cell contains a bit of data. Memory organized in such a fashion is called a xe2x80x9cmemory array.xe2x80x9d The data in each storage cell can have either a logic low value, i.e., xe2x80x980,xe2x80x99 or a logic high value, i.e., xe2x80x981.xe2x80x99 As a result, the value(s) of one or more storage cells are often used to represent numbers, characters, instructions, etc. Accordingly, to ensure that data in a storage cell is properly read and stored, important consideration must be afforded to how a memory array is designed.
FIG. 2 shows a typical implementation of a memory array (20). The memory array (20) has numerous storage cells (also known and referred to as xe2x80x9cmemory elementsxe2x80x9d) (22), where each storage cell (22) is connected to a bit line (also known as xe2x80x9crow linexe2x80x9d) (24) and a word line (also known as xe2x80x9ccolumn linexe2x80x9d) (26). A storage cell (22) is selected for a read/write operation by some combination of activating the bit line (24) connected to the storage cell (22) and activating the word line (26) connected to the storage cell (22).
Accurately and quickly reading data from a memory array, such as the one shown in FIG. 2, is challenging because of both large physical sizes of the memory array and a high number of entries, i.e., storage cells, in the memory array. A typical implementation used by designers to increase read operation performance is to pre-charge a bit line to a logic high value, i.e., xe2x80x981,xe2x80x99 prior to a read operation (also referred to as xe2x80x9cpre-charge phasexe2x80x9d), and then to perform, i.e., evaluate, the read operation (also referred to as xe2x80x9cevaluation phasexe2x80x9d) on a particular storage cell by allowing the bit line connected to the particular storage cell to discharge if the particular storage cell holds a xe2x80x980xe2x80x99 value. If, however, the bit line does not discharge, it implies that the particular storage cell connected to the bit line holds a xe2x80x981xe2x80x99 value. Therefore, reading a xe2x80x981xe2x80x99 takes relatively no time to evaluate because the bit line is already pre-charged to a xe2x80x981.xe2x80x99 However, reading a xe2x80x980xe2x80x99 is more time-intensive because the bit line, which is long and loaded in a large memory array, has to discharge from to a logic low value from a logic high value in order for the read operation to evaluate to a xe2x80x980.xe2x80x99
One approach used by designers to increase read operation performance involves pre-charging a bit line to some intermediate value between logic low and logic high in order to reduce the amount of charge that needs to be discharged during an evaluation phase (this approach is referred to as xe2x80x9csense amplifier approachxe2x80x9d). Although this approach results in faster read operations than in cases where the bit line is pre-charged to a logic high value, this approach requires sensitive circuitry that is prone to malfunction due to unexpected but likely fabrication and environment variations.
Another approach used by designers to increase read operation performance involves dividing a bit line into smaller xe2x80x9clocalxe2x80x9d bit lines as opposed to using a continuous bit line (hereinafter xe2x80x9cfull-railxe2x80x9d) for the read operation (this approach is referred to as xe2x80x9csplit bit line approachxe2x80x9d). The local bit lines, through some circuitry (discussed below with reference to FIG. 3), are connected to a xe2x80x9cglobalxe2x80x9d bit line. Because the storage cells are connected to the local bit lines, the global bit line is less loaded. However, this approach is relatively slow because the global bit line can discharge through only one path opened by one local bit line. In other words, if a storage cell contains a xe2x80x980,xe2x80x99 and that storage cell is then read, the local bit line connected to the storage cell must discharge before the global bit line can discharge. This approach is less prone to malfunction than the sense amplifier approach discussed above.
Regarding the split bit line approach discussed above, FIG. 3 shows a typical implementation of discharge devices (30) that are used to connect local bit lines (32) to a global bit line (34). During an evaluation phase of a read operation, if a storage cell (36) holding a xe2x80x980xe2x80x99 value is evaluated, the local bit line (32) associated with the storage cell (36) signals the discharge device (30) connected to the local bit line (32) to discharge the global bit line (34) connected to that discharge device (30). In this case, the global bit line (34) is discharged, i.e., driven low, by one discharge device (30). Although this implementation results in less load on a global bit line, this implementation is slow because a discharge device along the global bit line has to be designed to individually discharge portions of the global bit line that are not directly connected to the discharge device. It follows that this implementation results in slower memories and consequently, slower computer systems.
According to one aspect of the present invention, a memory array having a global bit line comprises a discharge device connected to the global bit line and a feedback path from the global bit line to another discharge device connected to the global bit line.
According to another aspect, a method for performing a memory array operation comprises discharging a local bit line, using a pull down stage to discharge a global bit line when the local bit line discharges, and using feedback from the global bit line to another pull down stage to cause the another pull down stage to further discharge the global bit line.
According to another aspect, a structure for a bit line comprises at least one discharge device connected to the bit line, at least one memory element connected to the at least one discharge device, and a feedback path from the bit line to another discharge device connected to the bit line.
According to another aspect, a discharge device for a memory array comprises a pre-charge node, logic connected to at least one local bit line, where a value on the pre-charge node sets the logic during a pre-charge phase, and a global internal node, where a value on the global internal node is set by the logic.
According to another aspect, a bit line structure for a memory array comprises a discharging means for discharging a bit line using a discharge device, and a feedback means for further discharging the bit line when the discharging means discharges the bit line.
According to another aspect, a method for discharging a bit line using multiple discharge paths comprises discharging the bit line through a discharge path provided by a discharge device connected to the bit line, and further discharging the bit line through another discharge path provided by another discharge device connected to the bit line, where feedback from the bit line signals the another discharge device to further discharge the bit line.
According to another aspect, a method for discharging a bit line using multiple discharge paths comprises a discharging step for discharging the bit line through a discharge device, a feedback step for signaling another discharge device, and another discharging step for further discharging the bit line through the another discharge device.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.